REPLACING SOVIET/RUSSIAN 556-SERIES ROM ICS WITH FPGA TECHNOLOGY: THEORETICAL BASIS, IMPLEMENTATION METHODOLOGY, SIMULATION-BASED FUNCTIONAL VERIFICATION

 

УДК 621.38

ABSTRACT

Following the discontinuation of Soviet semiconductor manufacturing lines, high-reliability radar and control systems built on 556-series bipolar TTL Schottky PROMs face acute component supply problems. This paper proposes a systematic six-stage methodology for replacing such ROM ICs with FPGA Block RAM, preserving the original socket interface, electrical levels, and external logic on the legacy board. The methodology integrates pinout-aware data extraction, memory-map consolidation, datasheet-based end-to-end timing budgeting with three documented mitigation options, and tri-state output management. A case study consolidating five 556РТ5/556РТ7А ROM ICs (7 KBytes total) into a single Xilinx Artix-7 XC7A35T achieved 100% bit-accurate correspondence across all 7,168 byte addresses, verified through 9,234 functional checks across eight behavioral simulation scenarios in Vivado XSIM 2022.1, with datasheet-projected reductions of 55.8% in PCB area and 81.3% in power consumption, and access time improved from 150–450 ns to 12–18 ns. The methodology, demonstrated on a Xilinx Artix-7 device, is conceptually portable to other FPGA vendors and applicable to other Soviet IC families.

АННОТАЦИЯ

Прекращение производства советских ТТЛ-Шоттки ПЗУ серии 556 создаёт острую проблему обеспечения комплектующими для высоконадёжных радиолокационных систем и систем управления. Предложена систематизированная шестиэтапная методика замены таких ПЗУ на блочную память ПЛИС с сохранением исходного интерфейса панелей, электрических уровней и внешней логики оригинальной платы. Методика включает извлечение данных с учётом цоколёвки, консолидацию карты памяти, сквозной расчёт временно́го бюджета по технической документации с тремя вариантами смягчения ограничений и управление выходами с тремя состояниями. На практическом примере пять ПЗУ 556РТ5/556РТ7А (7 Кбайт) консолидированы в одной ПЛИС Xilinx Artix-7 XC7A35T; в поведенческом моделировании достигнуто 100 %-ное побитовое соответствие по всем 7168 байтовым адресам, подтверждённое 9234 функциональными проверками в восьми сценариях поведенческого моделирования в среде Vivado XSIM 2022.1, расчётное сокращение площади платы — 55,8 %, энергопотребления — 81,3 %, а время доступа улучшено с 150–450 до 12–18 нс. Методика, реализованная на ПЛИС Xilinx Artix-7, концептуально переносима на ПЛИС других производителей и применима к другим сериям советских интегральных микросхем.

 

Keywords: FPGA, ROM, 556-series, obsolete component replacement, Block RAM, adapter board, legacy systems.

Ключевые слова: ПЛИС, ПЗУ, серия 556, замена устаревших компонентов, Block RAM, адаптерная плата, унаследованные системы.

 

1. INTRODUCTION

During the 1970s–1990s, the Soviet electronics industry developed and mass-produced numerous integrated circuit families to its own standards, serving military, industrial, and aerospace systems. The 556-series comprises one-time programmable (OTP) bipolar TTL Schottky ROMs that were extensively deployed in control systems, radar stations, and navigation equipment - most notably the 556РТ5 (512×8-bit organization) and 556РТ7A (2K×8-bit) [1].

Most weapons and military equipment systems currently in service were developed in the 1970s–1980s based on third-generation integrated circuits of small and medium scale of integration. The component base used in these systems is now both morally and physically obsolete, and the original manufacturing lines have largely been discontinued [2]. Consequently, the replacement of obsolete component base with modern VLSI and System-on-Chip solutions has been recognized as essentially the only economically justified path for sustaining the combat readiness of legacy radar, navigation, and control systems [3]. The technical characteristics of domestic FPGAs applicable to such modernization tasks have been analyzed by Karmanov et al. [19]. The technique commonly referred to as «свёртка» (consolidation) — wherein multiple legacy ICs are integrated into a single modern device while preserving the form-factor of the original Typical Replacement Element (ТЭЗ) — is particularly attractive for high-reliability applications such as radar controllers, navigation equipment, and industrial process control systems, which cannot be easily redesigned.

Field-Programmable Gate Array (FPGA) technology offers a viable solution: it allows the functional replication of multiple ROM ICs within a single device while preserving complete electrical, timing, and functional compatibility with the original system [3], [4]. The objective of this work is to develop and experimentally verify a systematic method for replacing 556-series ROM ICs with FPGA Block RAM. Specific tasks include: characterizing the 556-series ICs; formulating a six-stage replacement procedure; and practical validation through a case study replacing five ROM ICs with a single FPGA.

2. MATERIALS AND METHODS

2.1. Characteristics of 556-Series ROM ICs

The 556-series devices are one-time programmable ROMs based on bipolar TTL Schottky technology, designed to store firmware, lookup tables, character code tables, and computational coefficients [1]. Key parameters are summarized in Table 1.

Table 1.

Key parameters of 556-series ROM ICs

Parameter	556РТ4	556РТ5	556РТ7A	556РТ8
Organization	256×8	512×8	2K×8	2K×8
Capacity	2 Kbit	4 Kbit	16 Kbit	16 Kbit
Address lines	8	9	10	11
Data lines	8	8	8	8
Supply voltage	+5V	+5V	+5V	+5V
Logic family	TTL	TTL	TTL	TTL
Access time (ns)	150–450	150–450	150–450	150–450

 

Approximate Western equivalents exist: 556РТ5 corresponds loosely to the Intel 3604 [5], and 556РТ7A to the 82S191 [6]. However, the equivalence is not exact with respect to electrical and timing parameters, and careful verification is required when substituting.

2.2. FPGA Technology and ROM Replacement Capability

An FPGA is a digital IC whose hardware configuration can be reprogrammed after manufacture. A modern FPGA typically contains configurable logic blocks (CLBs), Block RAM, DSP multiplier blocks, and configurable I/O standards [3], [4].

Block RAM is the key element for ROM replacement. It can be configured as a ROM by initializing fixed content at configuration load time and permitting only read operations. An entry-level FPGA typically provides 18 Kbit to several hundred Kbit of Block RAM [3],[4]; the architecture and Block-RAM characteristics of domestic 5578-series FPGAs are described in [20] - sufficient to store the data of dozens of 556-series ROM ICs.

The advantages of the FPGA solution over sourcing original replacement ICs include: consolidation of multiple ICs into a single device; ability to update ROM data by reloading the bitstream; abundant and stable component supply; reduced PCB area and power consumption; and improved reliability through the use of new components.

2.3. Principle of ROM-to-FPGA Mapping

The fundamental principle is to map the address and data spaces of multiple physical ROM ICs into a unified memory space within the FPGA Block RAM [7]. The architecture comprises three functional blocks: (1) a chip-select (CS) decoder that receives CS signals from the original board and computes the corresponding address offset; (2) a ROM memory block implemented with Block RAM, initialized with data extracted from the original ICs; (3) an output controller managing the high-impedance (Hi-Z) state on the data bus when no chip is selected. The internal FPGA address is computed as:

ADDR_internal = BASE_OFFSET(CSᵢ) + ADDR_external

where BASE_OFFSET(CSᵢ) is the base address of the i-th IC in the memory map, and ADDR_external is the address input from the original board.

2.4. Six-Stage ROM-to-FPGA Migration Procedure

The proposed procedure is structured into six stages, each with clearly defined inputs, outputs, and completion criteria.

Stage 1: Survey and Data Acquisition

a) Original board analysis. Identify the exact IC part numbers, quantities, physical locations, and functional roles of all ROM ICs on the original board. Reconstruct or trace the original schematic, documenting all pin connections of each ROM IC to the address bus, data bus, and control signals.

b) ROM content extraction. Remove each IC from the board and mount it in a dedicated EPROM/PROM programmer (ST-007) [8]. Read each IC at least three times and compare results to verify data integrity [9]. Save contents as binary files (.bin) with an unambiguous naming convention.

c) Timing signal measurement. Using an oscilloscope or logic analyzer, measure signals on the operating board to record: actual access times, CS/OE-to-valid-data timing relationships, ROM access frequency, and access patterns (simultaneous vs. sequential).

Stage 2: FPGA Solution Design

a) FPGA selection criteria: sufficient Block RAM capacity for all ROM data; adequate I/O count; 5V logic compatibility (or level-shifter provision); appropriate temperature range; non-volatile internal configuration capability.

b) Memory map construction. Assign each original ROM IC a distinct address region within the FPGA memory space. Preserve the external interface - each IC retains its own CS signal. An internal CS decoder translates these signals into internal addresses.

c) RTL design (VHDL/Verilog). Design the top-level module with three functional blocks: a CS decoder; a Block RAM ROM block; and a tri-state output controller. RTL code must be fully commented and comply with project coding standards.

d) Memory content initialization. The binary content extracted from the 556РТ5 and 556РТ7A ROM ICs is converted into a hexadecimal text format (.hex), in which each line represents one memory word in ASCII hexadecimal notation. The .hex file is loaded into the Block RAM of the Artix-7 FPGA. This approach ensures bit-for-bit accuracy with respect to the original Soviet ROM content and enables direct manual inspection of the data prior to FPGA programming.

Stage 3: Simulation and Verification

Write a comprehensive testbench covering: sequential full-address sweep for each virtual ROM IC (100% match required); chip-select isolation; Hi-Z verification; and timing checks. Simulation results are automatically compared by script.

Stage 4: Adapter Hardware Design

Design an adapter PCB carrying the FPGA with connectors that are pin-compatible with the original IC sockets. Key components include: the FPGA with internal configuration flash; 5V↔3.3V level shifters (SN74LVC2T45 [10]); an LDO voltage regulator generating 3.3V from 5V; 100 nF bypass capacitors; and a JTAG header for configuration reloading.

Stage 5: Programming and System Testing

Load the bitstream into the FPGA via JTAG, preferably into internal flash for autonomous boot. Bench testing: verify power rails, probe signals with a logic analyzer, and compare FPGA responses against reference data. Functional system testing: operate the system with the adapter board, observe all operating modes, and compare output signals against the reference baseline.

Stage 6: Documentation and Handover

Prepare complete technical documentation: IC-to-FPGA memory region cross-reference table; schematic and Gerber PCB files; annotated RTL source code; memory initialization and original binary files (with SHA-256 checksums); test report; FPGA programming instructions; and Bill of Materials (BOM).

3. RESULTS AND DISCUSSION

3.1. Case Study

The verification case study was conducted on a dedicated signal processing board in which five 556-series ROM ICs serve as precomputed data lookup tables (no processor code). ROM addressing is performed entirely by external combinational and sequential logic; no CPU is involved. Such precomputed-LUT architectures remain in use in modern wideband radio-signal-processing implementations [21]. The IC configuration is presented in Table 2.

Table 2.

ROM IC configuration on the original board

IC	Type	Organization	Capacity	Function
U1	556РТ5	512×8	4 Kbit	Sine lookup table (512 samples)
U2	556РТ5	512×8	4 Kbit	Cosine lookup table (512 samples)
U3	556РТ7A	2K×8	16 Kbit	FFT twiddle factors
U4	556РТ7A	2K×8	16 Kbit	Hamming/Hann window coefficients
U5	556РТ7A	2K×8	16 Kbit	7-segment LED decoder table

 

Total capacity: 2×4 + 3×16 = 56 Kbit (7 KBytes). The FPGA selected is the Xilinx Artix-7 XC7A35T-1CPG236I [4]: 1,800 Kbit Block RAM (50 × RAMB36E1), 33,280 logic cells, 106 I/O pins, industrial temperature range (−40°C to +85°C), supported by Vivado Design Suite [11]. For hardware deployment, an adapter board with 5V↔3.3V level shifters is required. The proposed adapter is a 4-layer, 55 mm × 45 mm PCB including: the FPGA in CPG236 BGA package; three 74LVC245 ICs for level shifting [10]; three LDO regulators (AMS1117-3.3, MIC5219-1.8YS, TLV62569 for 1.0V); a Micron N25Q064A SPI configuration flash; a 100 MHz CFPS-72 crystal oscillator; five DIP-24 connectors; and a 14-pin JTAG header. The projected performance comparison is presented in Table 3.

Table 3.

 Projected comparison: original vs. FPGA-based solution

Parameter	Original (5 ICs)	FPGA Solution
Number of ICs	5	1 (+ 3 level shifters)
PCB area	~56 cm²	24.75 cm² (−55.8%)
Power consumption	4.275 W	0.8 W (−81.3%)
Access time	150–450 ns	12–18 ns
Updatability	No (OTP ROM)	Yes (reprogram)
Component availability	Discontinued	Readily available
Data accuracy	Reference	100% match
Reliability	Aging ICs	New components

         

Specifically, the three 556РТ7A ICs consume 5 V × 185 mA × 3 = 2775 mW, while the two 556РТ5 ICs consume 5 V × 150 mA × 2 = 1500 mW, yielding a total power consumption of 4.275 W for the five original ROM ICs. By comparison, the Xilinx Artix-7 XC7A35T FPGA consumes approximately 0.8 W, and the three 74LVC245A buffer ICs consume merely 0.13 mW × 3 ≈ 0.4 mW. Consequently, the proposed FPGA-based solution reduces the overall power consumption by approximately 81% compared to the original implementation.

 

Figure 1. Connection diagram of the converter circuit

 

3.2. External Logic

Since the ROM ICs serve exclusively as lookup tables, address generation and chip selection are performed entirely by external logic on the original board: a 10-bit binary counter 1533ИЕ7 (≡74ALS193) scanning the sample index; a 3-to-8 decoder 1533ИД7 (74ALS138) generating five CS signals; two 4-bit comparators 1533СП1 (74ALS85) detecting quarter-cycle boundaries; an 8-bit D-flip-flop register 1533ИР22 (74ALS374) latching ROM data at 10 MHz; and NAND/NOR gates (133ЛА3, 133ЛЕ1) for control timing. All external logic operates at 5V TTL levels and remains physically on the original board in the FPGA replacement solution. The adapter replaces only the five ROM ICs and must replicate the electrical and timing behavior expected by the external logic (Figure 1). In particular, FPGA data output must be stable within 25 ns of an address change to satisfy the latch setup window.

3.3. RTL Design

The RTL description is divided into four VHDL modules (Listings 1–4).

Listing 1. Top-level entity declaration (rom_556_replacement.vhd)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity rom_556_replacement is

generic (

ROM_INIT_FILE : string := "rom_data.hex"

);

port (

        clk  : in  std_logic;

        CS_n : in  std_logic_vector(4 downto 0);

        OE_n : in  std_logic;

        ADDR : in  std_logic_vector(10 downto 0);

        DATA : out std_logic_vector(7 downto 0)

    );

end entity;

 

architecture rtl of rom_556_replacement is

    signal int_addr : unsigned(12 downto 0) := (others => '0');

    signal data_q   : std_logic_vector(7 downto 0) := (others => '0');

    signal cs_n_q   : std_logic_vector(4 downto 0) := (others => '1');

    signal oe_n_q   : std_logic := '1';

    signal any_cs_q : std_logic;

 

begin

    -- The CS decoder (Listing 2), BRAM read (Listing 3),

    -- and output controller (Listing 4) are instantiated here.

end architecture rtl;

Listing 2. CS decoder (cs_decoder.vhd)

cs_decode : process(CS_n, ADDR)

variable base_v : unsigned(12 downto 0);

variable off_v  : unsigned(12 downto 0);

begin

  base_v:= (others => '0');

  off_v := (others => '0');

  if CS_n(0) = '0' then -- U1:556РТ5 , 512B, base=0x0000, 9-bit addr

     base_v := to_unsigned(16#0000#, 13);

     off_v  := "0000" & unsigned(ADDR(8 downto 0));

  elsif CS_n(1)='0' then --U2: 556РТ5 , 512B, base=0x0200, 9-bit addr

     base_v := to_unsigned(16#0200#, 13);

     off_v  := "0000" & unsigned(ADDR(8 downto 0));

  elsif CS_n(2)='0' then --U3: 556РТ7А, 2KB, base=0x0400, 11-bit addr

     base_v := to_unsigned(16#0400#, 13);

     off_v  := "00" & unsigned(ADDR(10 downto 0));

 elsif CS_n(3)='0' then --U4: 556РТ7А, 2KB, base=0x0C00, 11-bit addr

     base_v := to_unsigned(16#0C00#, 13);

     off_v  := "00" & unsigned(ADDR(10 downto 0));

 elsif CS_n(4)= '0' then --U5: 556РТ7А, 2KB, base=0x1400, 11-bit addr

     base_v := to_unsigned(16#1400#, 13);

     off_v  := "00" & unsigned(ADDR(10 downto 0));

end if;

 int_addr <= base_v + off_v;

end process cs_decode;

Listing 3. Block RAM ROM module (rom_block.vhd)

generic (ROM_DEPTH : integer := 7168);

type rom_t is array (0 to ROM_DEPTH-1) of std_logic_vector(7 downto 0);

 

impure function init_rom_from_file(filename : in string)

return rom_t is

file     rom_file : text;

variable rom_line : line;

variable rom_val  : std_logic_vector(7 downto 0);

variable rom_arr  : rom_t := (others => (others => '0'));

variable file_ok  : file_open_status;

 

begin

  file_open(file_ok, rom_file, filename, read_mode);

  if file_ok = open_ok then

     for i in 0 to ROM_DEPTH-1 loop  -- read only 7168 actual bytes

        exit when endfile(rom_file);

        readline(rom_file, rom_line);

        hread(rom_line, rom_val);

        rom_arr(i) := rom_val;

      end loop;

      file_close(rom_file);

  end if;

  return rom_arr;

      end function;

 

constant ROM_DATA:rom_t:= init_rom_from_file (ROM_INIT_FILE);

attribute rom_style : string;

attribute rom_style of ROM_DATA : constant is "block";

 

bram_read : process(CLK)

  begin

     if rising_edge(CLK) then

         data_q <= ROM_DATA(to_integer(int_addr));

     end if;

  end process bram_read;

Listing 4. Tri-state output controller (output_controller.vhd)

    ctrl_pipe : process(CLK)

begin

       if rising_edge(CLK) then

           cs_n_q <= CS_n;

           oe_n_q <= OE_n;

       end if;

end process ctrl_pipe;

 

any_cs_q <= not (cs_n_q(0) and cs_n_q(1) and cs_n_q(2) and cs_n_q(3) and cs_n_q(4));

DATA <= data_q when (oe_n_q = '0' and any_cs_q = '1') else (others => 'Z');

The CS decoder operates as pure combinational logic (Listing 2), while Block RAM reads are synchronous at 100 MHz (Listing 3), consistent with the RAMB36E1 primitive behavior. The tri-state output controller (Listing 4) drives the data bus only when a chip is selected and OE is asserted.

The control signals CS_n and OE_n are registered through the ctrl_pipe process to align tri-state transitions with the synchronous BRAM read pipeline, ensuring deterministic phase relationship between output-enable changes and the read clock and avoiding combinational glitches at high switching rates. This introduces a latency of one BRAM clock period (10 ns at 100 MHz) between the external CS/OE transition and the corresponding Hi-Z transition at the data pins. Because the case-study system operates at 10 MHz with the FPGA read clock phase-locked to it (Section 3.6), this latency is bounded and deterministic and does not produce bus contention with other devices on the data bus. In applications requiring fully asynchronous Hi-Z behavior identical to the original PROM — for example, fault-injection diagnostics that exercise sub-cycle CS transitions — the ctrl_pipe process can be omitted and the assignments can use CS_n and OE_n directly, at the cost of slightly higher susceptibility to combinational glitches.

3.4. Vivado Synthesis and Resource Utilization

The design was synthesized and implemented in Xilinx Vivado Design Suite 2022.1 targeting the XC7A35T-1CPG236I. Synthesis strategy: "Vivado Synthesis Defaults"; implementation strategy: "Performance_Explore". ROM content (7,168 bytes) was provided via a .hex file concatenating the five original IC binary images. Resource utilization after place-and-route is shown in Table 4.

Table 4.

 Xilinx Artix-7 XC7A35T resource utilization

Resource	Used	Available	Utilization (%)
Slice LUTs	17	20,800	0.08
Slice Registers (FF)	6	41,600	0.01
Block RAM Tile (RAMB36E1)	2	50	4.00
Bonded IOB	26	106	24.53
MMCM (clock)	1	32	3.13

 

3.5. Timing Closure

Timing constraints were defined in a Xilinx Design Constraints (.xdc) file. The primary clock is 100 MHz from a low-jitter crystal oscillator, multiplied to 200 MHz by the MMCM to drive the Block RAM read port. A virtual 10 MHz clock models the original system clock driving the 1533ИР22 latch, with set_input_delay and set_output_delay constraints enforcing the 25 ns setup requirement. After synthesis and implementation, the timing report (report_timing) must show non-negative WNS, TNS, and WHS for closure. The critical path runs from the ADDR input through the CS decoder combinational logic to the Block RAM address port. For the XC7A35T-1CPG236I speed grade −1, expected Block RAM access time is approximately 2–3 ns per DS181 [3].

3.6. Timing Budget Analysis

The 1533ИР22 latch (Section 3.2) imposes a 25 ns setup window: data at the latch input must be stable no later than 25 ns before the rising edge of the system clock that captures it. Because the 1533ИЕ7 counter, the ROM-replacement adapter, and the latch all share the same 10 MHz reference, the entire chain from address-bus transition to latch-stable data must close within this 25 ns window after the last beneficial clock alignment. To verify feasibility prior to physical prototyping, an end-to-end timing budget was constructed from manufacturer datasheets across the worst-case industrial corner (T_a = −40 to +85 °C, V_CC at minimum specified value).

 

Figure 2. Signal path and contributing delay segments

 

The signal path is decomposed into three concatenated stages (Figure 2). Stage I — asynchronous input path, from the original-board address bus to the BRAM address port: PCB trace t₁, the 74LVC245A 5 V → 3.3 V translator t₂, the FPGA input buffer t₃, and the routing plus combinational CS-decoder LUT t_lut feeding the BRAM address input. Stage II — synchronous BRAM read, clocked at 100 MHz by an MMCM that is phase-locked to the system 10 MHz reference; under phase-locked operation the BRAM rising edge is engineered to occur immediately after worst-case address arrival, so the contribution of this stage reduces to the BRAM clock-to-output delay T_CKO_B alone. Stage III — asynchronous output path, from the BRAM data port back to the latch input: FPGA output buffer t₅, the 74LVC245A 3.3 V → 5 V translator t₆, and PCB trace t₇.

The MMCM phase locking is not an optimization but a necessary condition for closure. If the 100 MHz BRAM clock were generated from an independent oscillator, the relative phase between the address-stable instant and the next BRAM clock edge would be unbounded over time and Stage II would have to be conservatively budgeted as one full BRAM clock period (10 ns) plus T_CKO_B, eroding the margin by approximately 10 ns. With the on-chip MMCM driven from the 10 MHz system reference, the BRAM sampling instant is deterministic relative to address arrival, and the residual contribution of Stage II is bounded by T_CKO_B with the BRAM input setup time absorbed into the input-path margin. Substituting datasheet worst-case values yields the budget summarized in Table 5.

Table 5.

Address-to-data-valid timing budget

Stage	Segment	Element	Typ. (ns)	Max. (ns, industrial)	Source
I	t₁	PCB trace (in)	0.5	0.8	calc.
	t₂	74LVC245A 5→3.3V	3.8	8.1	[10]
	t₃	FPGA IBUF (LVCMOS33)	1.0	1.8	[3]
	t_lut	CS-decoder LUT + routing	0.5	1.0	[3]
II	T_CKO_B	BRAM clock-to-out	2.5	3.0	[3]
III	t₅	FPGA OBUF (LVCMOS33, 12 mA)	1.5	2.5	[3]
	t₆	SN74LVC2T45 3.3→5V	3.8	8.1	[10]
	t₇	PCB trace (out)	0.5	0.8	calc.
	Total		13.6 ns	26.1 ns

 

The typical-case total of 14.1 ns falls comfortably within the 25 ns setup window and is consistent with the 12–18 ns range quoted in the abstract. The worst-case total of 26.1 ns at the industrial corner, however, exceeds the budget by 1.1 ns and therefore requires margin recovery. Inspection of Table 5 shows that the two 74LVC245A translator stages (t₂ + t₆) account for 16.2 ns of the 26.1 ns worst-case total, identifying them as the dominant timing bottleneck. Three mitigation options were considered:

(a) Speed-grade upgrade. Migrating to the XC7A35T-2 (speed grade −2) reduces T_CKO_B by approximately 15 % and the IBUF/OBUF delays t₃ and t₅ by approximately 10 %, recovering ≈ 1.0 ns and yielding a worst-case total of ≈ 25.1 ns — at the boundary of the 25 ns budget.

(b) Faster level translator. Replacing the 74LVC245A with the SN74LVC2T45 (t__PD,max ≈ 4.5 ns at V_CCB = 3.3 V over the industrial range) reduces (t₂ + t₆) from 16.2 ns to ≈ 9.0 ns, yielding a worst-case total of ≈ 18.9 ns and providing 6.1 ns of margin. The TXS0108E auto-direction translator was also evaluated but rejected on the grounds of higher propagation delay and weaker output drive; the SN74LVCH16T245 is a viable alternative for 16-bit buses.

(c) Restricted temperature range. Constraining deployment to the commercial range (0 to +70 °C) lowers t__PD,max of the 74LVC245A from 8.1 ns to 6.3 ns, reducing (t₂ + t₆) by 3.6 ns and yielding a worst-case total of ≈ 22.5 ns with 2.5 ns of margin.

For the present case study, option (c) is selected: the adapter PCB retains the 74LVC245A translator and restricts deployment to the commercial range, yielding a worst-case total of 22.5 ns within the 25 ns latch-setup window. The 12–18 ns access-time range and 55.8 % PCB-area figure quoted in the abstract and Table 3 reflect this configuration. Applications inheriting Soviet military-grade temperature requirements (−60 to +85 °C) should adopt option (a) or option (b), with the corresponding cost and BOM trade-offs.

It must be emphasized that the figures in Table 5 are derived from datasheet specifications and not measured on hardware. Final timing closure will require post-layout simulation with extracted parasitics from the assembled adapter PCB, and on-board oscilloscope measurement of the address-to-data path under nominal and worst-case operating conditions; both fall outside the scope of the present paper and are listed in the Limitations (Section 3.9).

3.7. Comparison with Related Work

The problem of replacing obsolete parallel ROM/PROM ICs has been addressed in the literature through four broad categories of solutions, each with distinct trade-offs (Table 6).

Drop-in modern PROM/EEPROM substitution. The most direct approach uses currently-available JEDEC-standard parts - typically Atmel AT27C-series OTP EPROMs or AT28C-series EEPROMs - as pin-compatible replacements [12]. This works well for Western 27C-series sockets but is not applicable to Soviet 556-series ICs, which use a non-JEDEC pinout and bipolar TTL Schottky technology with no current Western equivalent. Even for 27C-compatible sockets, the long-term sustainability of this path is fragile: only one major vendor still produces OTP EPROMs and inventories continue to shrink.

SRAM-with-battery-backup emulator modules. Several open hardware projects (e.g., the SRAM/supercapacitor module of [13]) provide pin-compatible 27Cxxx replacements built from low-power asynchronous SRAM and a non-volatile retention mechanism. These modules retain the original socket footprint and operate at native 5V TTL levels, but require periodic re-charging or external programming, scale poorly when multiple ICs must be replaced (one module per socket), and again do not address Soviet-pinout devices.

Microcontroller-based EPROM emulators. Designs such as the EPROM-EMU-NG [14] and similar Arduino/ATmega-based projects emulate one or several 27Cxxx EPROMs using internal SRAM and GPIO bit-banging. While inexpensive and reprogrammable, the achievable access time is limited by the MCU clock rate and GPIO sampling latency, typically yielding effective access times of 50–200 ns - adequate for development boards but marginal for the 25 ns latch-setup window required by the case-study board. They are also constrained to 8-bit data widths and small address spaces.

FPGA-based legacy IC emulation. A growing body of work uses FPGAs to replace obsolete digital ICs [15, 16, 17]. Yu and Schaumont [15] address the security implications of FPGA replacement of aged components and propose pin-grounding schemes for hardware Trojan mitigation. Hallmans et al. [16] present an industrial case study of FPGA-to-FPGA replacement in a legacy control system, focusing on inter-vendor migration challenges. The EmbeddedBlox/MetroTech case [17] re-engineers a discontinued ST Microelectronics ZPSD peripheral using an Actel A3P060 FPGA with external voltage translators and Spansion flash, achieving 5V compatibility through a similar adapter-board approach to the present work; their final implementation consumed 42.5 mW versus 55 mW for the original IC.

Table 6.

Comparison of obsolete parallel ROM replacement approaches

Approach	Multi-IC consolidation	Soviet pinout	Access time	Reprogrammable	Native 5V
Drop-in modern PROM/EEPROM	No (1:1)	No	45–150 ns	OTP / EEPROM	Yes
SRAM + retention module	No (1:1)	No	35–55 ns	Yes (in-circuit)	Yes
MCU-based emulator	Limited (≤4)	Adapter	50–200 ns	Yes	Yes
FPGA-based (this work)	Yes (5:1)	Yes (custom adapter)	12–18 ns	Yes (JTAG)	Via level shifter

 

Position of the present work. The proposed solution differs from prior FPGA-based work in three respects. First, the target ICs (Soviet 556-series bipolar TTL Schottky PROMs) have no Western pin-equivalent and no available datasheet automation, requiring manual data extraction and pinout reconstruction from the original board. Second, the design replaces multiple heterogeneous ROM ICs (two 556РТ5 + three 556РТ7A, totalling 7 KBytes across five distinct chip-selects) with a single FPGA, rather than a one-to-one substitution. Third, the architecture preserves the external combinational and sequential logic on the original board (1533ИЕ7 counter, 1533ИД7 decoder, 1533ИР22 latch) unchanged, replacing only the ROM ICs at the socket interface — distinct from the more invasive board-redesign approach common in legacy modernization. Within this scope, a search of the IEEE Xplore, ScienceDirect, and eLibrary.ru databases indicates that peer-reviewed publications, in either English or Russian, specifically addressing the replacement of Soviet 556-series PROMs with FPGA technology remain limited. The methodology proposed in this paper aims to contribute to this area.

3.8. Verification Results

Functional verification was performed by behavioral simulation in Vivado XSIM 2022.1 against a golden reference reconstructed from the original ROM binary images. Two distinct coverage metrics were tracked. Data coverage measures bit-for-bit equivalence between DUT and reference across the address space and is reported as the number of byte addresses verified. Functional coverage measures correctness of operational behavior — chip-select decoding, output-enable response, tri-state contention, boundary conditions, and random-access patterns — and is reported as the number of independent assertions evaluated.

The testbench comprised eight scenarios (Table 7) yielding 9,234 functional assertions in total. Scenario 1 (sequential full-address sweep) provided complete data coverage by verifying all 7,168 byte addresses across U1–U5; scenarios 2–8 contributed an additional 2,066 functional assertions targeting CS decoding, tri-state behavior, random and boundary access patterns, checksum integrity, and propagation latency. All 9,234 assertions passed without deviation. The 32-bit additive checksum computed by the DUT (0x0008196E) matched that of the concatenated original ROM data, independently confirming bit-for-bit correspondence across the full 7,168-byte address space (Figure 3).

Table 7.

Breakdown of functional verification checks

No	Test scenario	Coverage type	Checks	Result
1	Sequential full-address sweep (U1–U5, all addresses)	Data + Functional	7168	Pass
2	Chip-select isolation (5 ICs × 4 states)	Functional	20	Pass
3	Hi-Z tri-state verification	Functional	4	Pass
4	Random access (16-bit LFSR)	Functional	1000	Pass
5	Rapid CS switching	Functional	1000	Pass
6	Boundary address checks	Functional	40	Pass
7	32-bit checksum integrity	Data	1	Pass
8	Propagation latency measurement	Timing	1	Pass
	Total		9234	All pass

 

Figure 3. Verification simulation results

 

3.9. Limitations and Future Work

The present study has three principal limitations that bound the scope of its conclusions and define the agenda for subsequent work.

First, the performance figures reported in this paper combine simulation-verified results with datasheet-based and tool-based projections. Specifically, the 100% bit-accurate data correspondence was directly verified through behavioral simulation in Vivado XSIM 2022.1, while access time, power consumption, and PCB area figures are projected from manufacturer datasheets, post-implementation timing and power reports, and geometric estimation, respectively. None of the projected figures has yet been verified on a fabricated prototype, and they should therefore be treated as design targets. Final timing closure, signal integrity on the 5 V↔3.3 V interface, and EMC compliance require physical verification that has not yet been performed.

Second, two functional differences from the original ICs are inherent to the FPGA implementation: a bitstream-loading delay at power-up that is absent in the original PROMs, and a priority-encoded chip-select decoder that masks rather than reproduces bus-contention behavior under simultaneous multiple-CS conditions.

For the proposed adapter design (XC7A35T configured from an N25Q064A SPI flash via Master SPI x1 mode at 50 MHz), the bitstream of approximately 17.5 Mbit [18] results in a configuration time of roughly 250–350 ms before the FPGA outputs become valid; this can be reduced to approximately 80–100 ms using Master SPI x4 mode if supported by the board layout. By contrast, the original 556-series PROMs are valid within microseconds of VCC stabilization. This delay is inconsequential in systems that perform power-on initialization or self-test sequences exceeding one second, but may be critical in systems with watchdog timeouts shorter than 200 ms or with strict boot-time bus access requirements. In such cases, applications can mitigate the delay by holding the system reset signal until the FPGA DONE pin is asserted, or by selecting a flash-based FPGA family (e.g., Microsemi IGLOO series) at the cost of higher unit price.

The priority-encoded chip-select behavior, by contrast, is inconsequential under nominal operation but may require attention in fault-injection-based diagnostics.

Third, the design has not been characterized across the full operating temperature range. The XC7A35T-1CPG236I is qualified for industrial ambient (−40 to +85 °C); applications inheriting Soviet military-grade requirements (−60 to +85 °C) may require migration to the −1Q or −1M speed grade. Subsequent work will address these gaps through fabrication and bench-characterization of the adapter PCB, EMC pre-compliance measurement, and temperature-cycle testing across the qualified operating range.

4. CONCLUSION

This paper has proposed and simulation-verified a systematic six-stage methodology for replacing legacy 556-series Soviet/Russian ROM ICs with FPGA Block RAM. The methodology preserves the original socket interface and external logic on the legacy board, enabling 'consolidation-style' (свёртка) modernization without invasive board redesign — a critical feature for high-reliability systems where full re-certification is prohibitively expensive.

Beyond the specific 556-series case, the proposed framework — encompassing pinout-aware data extraction, memory-map consolidation, end-to-end timing budgeting, and tri-state output management — is directly applicable to other Soviet IC families (К573, К541, К155 series) and to migration toward domestic Russian FPGAs (e.g., the 5578 series characterized in [20]) where component-origin constraints apply.

Subsequent work will focus on: (i) fabrication and bench characterization of the adapter PCB, including post-layout timing closure and EMC pre-compliance measurement; (ii) extension to Soviet RAM and ALU-class ICs; (iii) construction of an open IP core library of common Soviet logic primitives; and (iv) automated RTL generation from binary ROM dumps.

Acknowledgments

This work was supported by the Institutional-level research project: “Research on the design and manufacture of a functional testing device for the specialized digital computer on the Su-30MK2 fighter aircraft”, No. 25.TMX.06.

Declarations

All authors declare that they have no conflicts of interest.

 

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