RESEARCH ON DESIGN AND MANUFACTURE OF DIGITAL IC TEST EQUIPMENT BASED ON FPGA

 

ABSTRACT

The paper presents the design and fabrication process of a low-cost, reconfigurable automatic device for testing the functions of digital electronic components. The device is controlled via an application software running on a personal computer. The input stimulus signal values for the components under test are predefined and stored in the computer's database, then loaded into the device’s sample memory via a USB connection. These signals are deployed by the peripheral device to the input pins of the component under test (DUT - Device Under Test). The output signals from the DUT are compared with the sample values of a known-good element of the same type, which had been previously sampled, to determine whether the DUT is still functioning correctly. The study's results have been successfully applied to assist in diagnosing and detecting faults in digital logic ICs.

АННОТАЦИЯ

В статье представлены разработка и процесс изготовления недорогого реконфигурируемого автоматического устройства для тестирования функций цифровых электронных компонентов. Устройство управляется прикладным программным обеспечением, работающим на персональном компьютере. Значения входных сигналов стимулирования для тестируемых компонентов заранее определены и сохранены в базе данных компьютера, а затем загружены в память образца устройства через USB-соединение. Эти сигналы периферийное устройство подает на входные контакты тестируемого компонента (DUT – Device Under Test). Выходные сигналы DUT сравниваются с эталонными значениями заведомо исправного элемента того же типа, который был протестирован ранее, для определения корректности работы DUT. Результаты исследования были успешно применены для диагностики и обнаружения неисправностей в цифровых логических микросхемах.

 

Keywords: Automated testing equipment, database, IC, FPGA.

Ключевые слова: Автоматизированное испытательное оборудование, база данных, ИС, ПЛИС.

 

1. Introduction

In Vietnam, most technical equipment and military hardware, including many electronic devices, originates from Russia. Maintaining and upgrading these systems requires frequent maintenance, repair, or replacement of electronic components. The malfunction of many devices-especially those with aged components-creates tasks for maintenance personnel, placing them in situations where rapid repair or replacement is necessary to ensure the system's proper functioning. The repair process of an electronic device involves multiple steps and must be carried out by highly skilled and experienced technicians. It typically starts with checking the device modules and damaged circuit boards to identify the faulty components for replacement. Many components have specialized functions and are manufactured by different companies. In reality, using components with equivalent functions to replace those on military equipment circuit boards is tricky, as authorized organizations and experts must inspect and approve them. Therefore, the simplest solution for repairing military equipment is to find and purchase the exact components damaged on the circuit boards for direct replacement. However, sourcing and ordering components from Russia has become increasingly complex and time-consuming, as the procurement process often requires months of lead time. This presents a significant challenge for repair units, which are typically forced to purchase components in bulk to reduce costs and minimize waiting time. As a result, many components purchased long ago remain unused. Due to poor storage conditions, they are prone to failure or may not operate reliably when integrated into circuit board systems. Currently, specialized testing equipment for Russian digital electronic components is not popular. Some existing equipment in the country and abroad includes LEAPER-2 of LEAPTRONIX [1], or GUT-6000B [2] of GW Instek. The above equipment is designed to test many types of capacitor ICs. It has a closed database, is not compatible with most packaging standards for Russian ICs, so it isn't easy to use for Russian components, and has a very high cost. The power supply pin for the tested IC is fixed or uses the logic signal directly from the microcontroller to supply power, making the equipment unstable when operating for a long time. In this article, the authors target the testing object of Russian digital electronic components (including logic gates, counters, Flip-Flops, buffers, multiplexers, demultiplexers, etc.). Still, the research results can be widely applied to many other popular digital ICs, including capitalist ICs. The authors present the process of designing and manufacturing a testing device, including management and control software on the computer, firmware embedded in an FPGA (Field-Programmable Gate Array) on the circuit board, and peripheral devices connected to the testing IC via a socket. The difference compared to the devices that have been studied with similar functions [1-5] is that the device is built with software and a database organized to allow users to create standard libraries for each type of IC to be tested. The device can test components with different functions without changing the hardware, but it only needs to be reconfigured through software. The test results can report damage to the IC pin position. The test interface is intuitive, easy to operate, and cheaper than similar products.

The paper has four sections: section 2 discusses the system design, section 3 describes the experimental results, and section 4 is the conclusion and summary.

2. System design

2.1. Technical feature requirements

To meet practical requirements, some critical criteria need to be considered when building a testing device as follows:

- The device is capable of detecting errors on Russian ICs coded 133/134/136, TTL 74/54, CMOS 40/45 (including logic gates, counters, Flip-Flops, buffers, multiplexers, demultiplexers, etc.), and SelfTest.

- The device supports 2 voltage levels (5V and 3.3V) to meet TTL or CMOS standard ICs appearing on electronic circuit boards, test ICs with up to 20 pins.

- Automate the testing of digital ICs, error notifications, and error locations.

- The ability to allow users to create test libraries for each type of IC on the software.

- The software's friendly graphical interface helps users operate and understand the testing process efficiently. The library creation, control, and information display functions are designed clearly and intuitively. Support provides users with diagrams and text instructions to perform the necessary operations.

 

Figure 1. Overview structure of IC testing equipment system

 

2.2. General structure diagram of the system

Based on the requirements of the device's features, the general structure diagram of the device system is shown in Figure 1.

2.2.1. Hardware

The device's hardware plays an important role in performing the testing function. Building optimal hardware helps minimize risks and increase stability, improve the quality of testing for the device, and save costs. When implementing the hardware design, the team conducted simulations and test runs to ensure feasibility in the circuit board processing process.

Power block: Contains 5V and 3.3V power modules to supply power to the entire system.

Central processor: Contains a program logic processor for controlling and processing data from the test IC, with the primary function: receiving encoded data from the software, decoding and then deploying signals to the IC pins, receiving the IC output signal and encoding it to the computer, controlling other blocks in the system such as: amplifier block, voltage selection block, LCD and buzzer, ... supporting flexibility and customizing IC pin configuration as required.

USB to TTL communication block: Is the component connecting the hardware and software of the test device. The block receives encoded data packaged from the computer, transmits it to the FPGA for processing, and simultaneously transmits the data packet carrying the output information of the IC to be tested back to the computer, using the UART communication protocol for stable and reliable speed.

Voltage selection block for test IC: This block manages the selection of the appropriate voltage level for the specific IC being tested. It ensures a stable and accurate voltage source and supports two main voltage levels of 5V and 3.3V to meet a variety of ICs. This block receives control signals from the microprocessor to power the test IC.

Current amplifier block: This block increases the stability of the power supply signal from the central processor to the IC, ensuring logical accuracy during the test. This block receives control signals from the microprocessor and, combined with the voltage selection block, provides signals corresponding to the function to the pins of the test IC.

Voltage conversion circuit: This circuit converts and supplies voltage according to the test IC's requirements. It ensures compatibility with different voltage levels between the test IC and the central processor (FPGA).

10x2 IC SOCKET: Provides physical connection to the test IC via a 10x2 pin adapter, allowing flexibility in mounting ICs and working with various ICs.

Additional basic components include:

Pushbutton: Used to perform functions like starting a test or switching between modes.

Buzzer: Provides audible alerts to the user of important events during the test.

Display: Displays detailed information about the test process and results.

LED indicator: This device provides visual information with an LED light, helping the user monitor the status of each signal pin during the test.

2.2.2. Software and Database

The software and database are deployed and installed on a personal computer, which is connected to the testing device's hardware via a wired communication protocol standard. The graphical interface helps users easily interact with the device and provides functions for creating test libraries, controlling and displaying detailed information, and managing test results. The software structure of the testing device is shown in Figure 2.

 

Figure 2. Overview diagram of the software structure of the testing device

 

The software supports four main functions:

- Check and detect faulty Ics.

- Create standard libraries for each type of IC.

- View and edit created libraries.

- Manage and view test results.

There is also a user guide page for using the device and a contact page for users with problems that must be addressed.

2.3. Design of main blocks of testing equipment

2.3.1. Central processing block

The Artix 7 FPGA is a powerful chip to implement the test device functions, with extensive resources and reconfigurability of the FPGA ensuring flexibility in the testing and development process without changing the central part.

The 3.3V power block has been integrated on the FPGA module (Figure 3), so it can be taken advantage of to minimize the steps of designing the voltage regulator block for the 3.3V power supply.

 

Figure 3. Artix-7 FPGA module

 

2.3.2. Power supply block combined with USB-C communication port

The power source ensures the system operates stably and reliably when designing electronic devices. The proposed solution is to integrate a 5V power supply port with a communication port into the design, connecting directly to the software on the computer to ensure device performance management. This design optimizes the hardware to provide enough power for the device and optimizes the space for component placement. At the same time, this solution eliminates any voltage conflicts when using both USB and external power for the device simultaneously. Using a USB-C port not only meets the aesthetic needs with a compact size, but also brings convenience. The authors also integrate a power indicator light in the circuit, providing visual information when connecting and pressing the power button.

2.3.3. Voltage Selector for Test ICs

Based on the voltage requirements of the test ICs, the authors developed a converter that the central processor can control. This solution uses a 5V mini relay combined with additional components to create a flexible switching circuit between 5V and 3.3V voltages. It also protects against reverse voltage from the coil in the relay, minimizing negative impacts on the system. An LED is integrated to display the voltage being selected. In this way, the proposed solution not only meets the voltage switching requirements but also protects the system performance from potential problems.

2.3.4. IC to 3.3V Voltage Conversion Block

Regarding the issue of voltage compatibility when exchanging signals from ICs and central processors, a problem arises: FPGA is a central processor with an operating voltage of 3.3V according to the CMOS standard. In contrast, Russian ICs require 5V to operate according to the TTL standard. To avoid conflicts between the central processor of the device due to the direct connection between the output of the test IC (5V) and the input of the FPGA (3.3V) without a voltage conversion mechanism, the proposed solution is to use a 5V-3.3V voltage level converter IC with 16 channels capable of controlling the direction of data transmission. This helps ensure the stability and safety of the central processor in the device, preventing the risk of fire.

2.3.5. Current amplifier block and LED display logic status

By examining the pin structure diagram of different types of ICs, the authors found that it is impossible to accurately determine the power pins (VCC, GND) of the IC that need to be tested. This comes from the diversity of pin layouts for each type of IC. Therefore, it is difficult to determine the power pins of the IC accurately. The goal is to create a flexible testing device to configure pins to suit all types of ICs, including VCC, GND, CLK, DATA, and NC. During the design process, it is not feasible to directly use the signal from the IO pin of the FPGA to supply power to the pins of the tested IC. Although the IO logic pin of the FPGA can be compatible with the logic signal from the IC, it cannot provide enough current at the power pin for the IC to be tested. This is because the maximum current of the logic IO pin is usually only 20 mA, while a test IC such as the 133ИЕ2 requires at least 70 mA. Using a logic signal to supply power to the test IC can lead to voltage drops at the logic output of the FPGA, causing the processor to heat up, causing errors in the reading and writing of data, thereby reducing the stability and accuracy of the device. The authors designed a current amplifier circuit using MOSFET elements to meet this requirement. This circuit also integrates LEDs indicating the logic status at each pin of the test IC.

The peripheral circuit is designed in two layers with dimensions that ensure compactness and portability during use, deployment, and simulation in the Altium Designer environment, as shown in Figure 4.

 

Figure 4. Peripheral device board

 

2.3.6. Peripheral circuit operation

Starting the test process, the hardware will receive a data packet from the computer transmitted via the USB-TLL block to the FPGA [6] and then decode it, then deploy the logic signal and the power signal through the amplifier block to the corresponding pins of the IC. After some time (Timer), when the logic states of the tested IC have stabilized, the FPGA will collect data from the IC outputs through the voltage conversion block and then encode it to send to the software for further processing. The flowchart in Figure 5 describes the operation of a test cycle on the hardware.

 

Figure 5. Flowchart of peripheral circuit operation during a test cycle

 

2.4. Database and software design

The software design features a small database encrypted with a small capacity and allows users to build test libraries, ensuring openness. The software is developed in the Qt Creator environment, which includes many supporting libraries when programming [7, 8].

2.4.1. Main screen interface

The main screen is designed with a simple, intuitive interface, as shown in Figure 6.

 

Figure 6. Main screen interface

 

• Tools: contains functions

• Information: supports users

2.4.2. IC Test Interface and Results Observation

The IC test page includes three primary operations, as shown in Figure 7.

 

Figure 7. IC test operation interface

 

• Set up communication connection:

- Set up communication port properties (COM Port)

- Set up the baud rate

• Select IC to test:

- List of ICs in the library

• Test operations and display results:

- Allow users to select the test speed suitable for the test purpose

- Observe the specific test progress displayed in the horizontal bar

- Use the stop or continue button to pause or continue the test process

2.4.3. Standard Library Creation Interface

Different ICs have different pin layouts and functions. Therefore, the library creation process requires configuring the pins and scripting tests for each IC according to its function. The datasheet accompanying each IC contains all technical issues.

The library creation interface consists of two windows (Figure 8).

 

Figure 8. Attribute and pin configuration interface for test IC

 

Pin Configuration

• IC Properties:

- Declare the IC name

- IC PIN

- Manufacturing technology

- Function description, notes

• IC pin configuration:

- Select function for each pin of the IC: VCC, GND, CLK, DATA, NC

- The selection process will be in the "Display information" section.

• Display information: display the information of the IC that has been declared by the user, including attributes and pin configuration.

Create a test scenario

• Create a test:

The user assigns logic levels to signal pins ‘1’, ‘0’, and ‘Z’ by clicking on each pin position. The software will warn when there is a duplicate test.

• Display tests:

- Displays a list of created tests.

After creating enough tests and the user clicking save, all declared information and test data will be encrypted and saved as a .bin file, the file name being the same as the test IC name. The library creation operation is described in Figure 9.

 

Figure 9. Process of creating a standard library for the IC to be tested

 

2.4.4. Building a data encryption algorithm

With the requirement to optimize the transmission frame size and ensure accuracy and synchronization during the communication process, the authors have researched and proposed a data encryption solution for a test consisting of three parts. The model of a data packet containing encrypted information is shown in Figure 10.

 

Figure 10. Structure of a test data packet for an IC

 

• Configuration encoding byte for test IC:

 

Figure 11. Details of the configuration encoding byte for the IC

Information about the IC voltage level (bit 7):

“1xxxxxxx” shows the IC voltage level 5V.

“0xxxxxxx” shows the IC voltage level 3.3V.

Information about the number of pins of the IC (bits 5, 6):

“x00xxxxx” shows the 14-pin IC.

“x01xxxxx” shows the 16-pin IC.

“x10xxxxx” shows the 20-pin IC.

“x00xxxxx” shows the remaining cases about the number of IC pins.

The least significant 5 bits (bits 0 to 4) in the configuration byte contain information about the number of tests represented in binary so that the user can create up to 32 tests for 1 IC.

• Data area for coding the tests:

With the requirement that the device can test for ICs with up to 20 pins, the authors used 10 bytes to represent information about each pin's type and logic level. Figure 12 shows details about 10 bytes of coding for 1 test.

 

Figure 12. Details of 10 bytes of encryption for 1 test

 

Use 4bits to encode information for a pin of the test IC, specifically:

- 4 high-significant bits encode data of the left pin row.

- 4 low-significant bits encode data of the right pin row.

Encoding the IC pin type uses bits 7, 6 for the left pin row and bits 3, 2 for the right pin row:

“00xx” represents the IC's InPut pin.

“10xx” represents the IC's Output pin.

“01xx” represents the IC's Power pin.

“11xx” is an unknown case.

Encoding the logic level of the IC pin uses bits 5, 4 for the left pin row and bits 1, 0 for the right pin row:

“xx00” cannot determine the Logic level.

“xx01” represents the Logic level '1'.

“xx10” represents the Logic level '0'.

“xx11” represents the high impedance level 'Z'.

When the test library creation for an IC is completed, the number of built tests will form a data area of n × 10 bytes, where n is the total number of tests. Figure 13 shows the data area encoding the tests.

 

Figure 13. Details of the byte-encoded container for the tests

 

The user-declared test IC information is expressed in ASCII code from byte "(n x 10) + 1" onwards.

2.4.5. Software testing activities

Starting the test requires ensuring the IC has a database and is displayed in the IC library list. The testing operation on the software is as follows:

- Establish a connection to the hardware of the testing device by configuring the communication port.

- Select the IC to be tested, and information about the IC will be displayed. The user will confirm the information.

- Conduct the test and wait for the results.

The testing time will vary depending on the function and the number of tests that the user has created for each IC. The maximum speed is 10 tests per second.

The software continuously sends the tests, while the hardware receives the data, decodes it, and deploys the signal to the pins. After a test cycle, the software receives a packet from the hardware, compares it with the standard library or the encoded signal when the user creates the library, and concludes whether the IC is good or faulty. The test process is shown in the flowchart in Figure 14.

 

Figure 14. Flowchart of software testing algorithm

 

2.5. Firmware system design

The firmware system is designed with 10 main blocks with “ckht” synchronization pulse (50MHz) and “rst” reset signal shown in Figure 15:

- UART_CONTROLLER: Communication block with the computer.

- DOC_FIFO_RX: Block to read data from the communication buffer

- SAMPLING_FREQUENCY: Block to generate data decoding frequency

- TOP_DECODER: Block to decode data

- CHECKING: Block to check and detect errors

- ENCODER: Block to encode data

- GUI_FIFO_TX: Block to write data to the communication buffer

- LCD: Block to control the display screen

- DELAY: Block to create delay time

- Debounce_bnt: Block to eliminate push button noise

 

Figure 15. Complete connection diagram of the Firmware system

 

System operation:

The UART_CONTROLLER block receives a serial signal via the “uart_rx” pin, containing the encoded data of the test stored in the FIFO_RX buffer. When the FIFO_RX block has data, the DOC_FIFO_RX block reads the data at the frequency created by the SAMPLING_FREQUENCY block (1kHz) and sends it to the TOP_DECODER block. After receiving 10 bytes (1 test), the TOP_DECODER block decodes and deploys the control signal through 20 pairs of “c_p” signals to the hardware to assign the corresponding logic state to each pin of the IC, and at the same time, the “done” signal is active. The “done” signal is delayed and sent to the CHECKING block as a comparison signal. The purpose is to delay for some time before latching the logic state at each pin of the IC to ensure the most accurate received signals. After a delay, the CHECKING block compares the signals of the Output pins with the database to detect errors and sends the results to the LCD block for display. At the same time, the ENCODER block receives the test results and transmits them to the buffer at FIFO_TX, then sends them to the computer via serial transmission at the “uart_tx” pin of the UART_CONTROLLER block.

3. Testing

3.1. Object testing process

The user selects available tests corresponding to the ICs they want to test, or they can create a library for a new IC. The library creation process is intuitive through the button press to select the logic state at each pin of the IC. The tests will be encoded and then packaged into a database corresponding to an IC. The software sends encoded signals to the hardware and receives results from the hardware, then compares them with the created library and detects errors.

The authors have created a library and surveyed some Russian ICs with codes: 133ЛA4 (containing 3 NAND 3-input elements), 133TM2 (containing 2 D-type Trigger elements), 133ИM3 (4-bit full adder), and some capitalist ICs with codes: 74LS90 (4-bit binary counter), 74LS148 (8-to-3 encoder). The testing process for IC 133ЛA4 follows the following five steps:

Step 1: Determine the IC's power and signal pins by surveying the voltage, pinout, and function in the Datasheet.

Step 2: Declare properties and pin configuration:

Start the software, select the library creation function, declare the IC's properties in the "IC Properties" section, and click "Done" to display the information.

In the "Pin Configuration" section, click on each position of each pin. At this time, the list of pins appears: VCC, GND, CLK, DATA, NC. Select the corresponding type surveyed in step 1.

In the "Display information" section, check the declared information. When you confirm that it is correct, click "Next" to proceed to step 3.

Step 3: Build the tests:

Based on the functions and operating principles surveyed in step 1, it is necessary to assign the signal pins logic levels: '1' (blue), '0' (red), and 'Z' (gray) by clicking on the position of each pin until the appropriate state appears. Each test will correspond to the state where the IC is considered to be working properly. Click “Save Test” to save the test to the library.

With IC 133ЛA4, the author team created four tests. Click “Finish” to complete the library creation process.

Step 4: Connect the device:

Connect the computer software to the peripheral device and put the suspected faulty IC into the test SOCKET. Because the Russian IC has a special packaging standard, an additional converter, must be used to communicate between the IC and the test device.

Step 5: Test operation:

On the software's main screen, select the "Check IC" item. In the "Set up connection to hardware" item, select the COMx port and baud rate 19200bps, then click "Connect". Select the IC to be tested: 133ЛA4. The bin was just created. Information about the IC will appear in the lower corner of the screen.

In the "Check IC 133ЛA4" item, select the slow test speed (2 articles per second). Click the "Auto Run" button to start the test process. You can use the “Stop” button during the test to pause the process. Observe the signal status at each pin of the IC and the information displayed on the screen. Conclude whether the IC is faulty or good. The testing process for other ICs is also performed similarly through the above 5 steps.

3.2. Test results

• The test of the Russian IC code 133TM2 (containing 2 Trigger elements type D) works well, and the results are:

- The test speed is two tests per second, and the test completion takes 3 seconds.

- The peripheral device reports the test progress on the LCD screen, and the LED shows the corresponding logic status at each pin of the IC.

- The device reported that the IC 133TM2 has no errors.

To create a case of IC error, the authors isolated pin 8 of the IC from the SOCKET, and obtained the result that the device reported an IC error on the computer screen and the buzzer.

• Testing the Russian IC code 133ЛA4 (containing 3 NAND 3-input elements) with the typical case and the simulated error case, the results were:

The test speed was two tests per second, and the test completion took 2 seconds. Figures 16 and 17 show the test results of IC 133ЛA4.

 

Figure 16. Good IC 133ЛA4 test result

 

Figure 17. Test result of faulty IC 133ЛA4

 

• Testing the 74LS148 capital code IC (8 to 3 encoder) with normal and simulated error cases, the results are:

The test speed is two tests per second, and the test completion takes 5 seconds. Figures 18 and 19 show the test results of IC 74LS148. When detecting a faulty IC, the device will warn via a buzzer signal and display the specific location of the faulty pins on the computer screen.

 

Figure 18. Good test result of IC 74LS148

 

Figure 19. Test result of faulty IC 74LS148

 

The test results for 3 ICs 133TM2, 133ЛA4, 74LS148 (the results are presented above) and other ICs (133ИM3, 74LS90) all give accurate results when detecting good or faulty. The test has shown that the designed device works effectively, supports the testing and error detection on Russian IC elements and capitalist ICs with reliability, serves the repair of large functional boards and has significant improvements compared to other devices such as: compact device; flexible configuration management software; convenient system operation; indicates damaged ICs; easily changes the configuration and SOCKET type to test digital ICs with different packaging standards.

4. Conclusion

By researching and applying electronic and programming techniques, the authors have integrated hardware, firmware, and software technology to design and manufacture a diagnostic device that detects failures effectively and accurately. Including 01 peripheral device and 01 testing software installed on the computer with the following characteristics:

- Function: detect errors and determine the location of the faulty pin of the digital IC; SelfTest.

- Test IC type: Russian code 133/134/136; TTL 74/54; CMOS 40/45 (including logic gates, counters, Flip-Flops, buffers, multiplexers, demultiplexers, ...)

- Test voltage: 3.3V and 5V

- Test speed: up to 10 tests per second

- Survey and build a test library for 50 ICs.

Limitations:

Some limitations when researching the device can be mentioned, such as the fact that peripheral devices cannot operate independently without using software, and that the device does not support similar ICs.

Development direction:

Based on current specific conditions, such as the capabilities of semiconductor technology, communications, and strong support from programming and design environments, the group proposes some future research directions as follows:

- Overcome the above limitations.

- Expand the device's features with the ability to test 24-pin ICs with plug and paste standards.

- Optimize the computer testing software regarding communication, and integrate additional functions to support users.

- The research group develops a device to test functional circuit boards based on the digital electronic component testing device.

Acknowledgement

This article is supported by a Ministry Level Project at the Le Quy Don Technical University, with code number 2022.85.29.

Declarations

All authors declare that they have no conflicts of interest.

 

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